TTL COMPATIBLE INPUT FOR BIMOS CIRCUITS
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Del.icio.us| IP.com Number | IPCOM000005556D |
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| Dated | Oct 1, 1985 UTC | ||
| Size | 2 page(s) (78.1 KB) | ||
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Publication Summary
It is often desired to develop the input threshold voltage of Transistor-Transistor-Logic (TTL) of two bass-emitter voltages (V,,) on technologies other than TTL. Some technologies such as Power SIMOS which combine bipolar and MOS devices do not allow the bipolar devices to be referenced to ground, thereby making it difficult to achieve the TTL input voltage. This restriction is the result of a P type substrate serving as the output of the circuit, thereby limiting all epitaxial regions (PNP bases and NPN collectors) to a voltage level at or near the positive supply voltage.| Country | United States |
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| Language | English (United States) |
| Related Person(s) |
(AUTHOR) Byron G. Bynum (AUTHOR) David L. Cave |
| Copyright | Motorola Inc. October 1985 |
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MOTOROLA Technical Developments Volume 5 October 1985
TTL COMPATIBLE INPUT FOR BIMOS CIRCUITS
by Byron G. Bynum and David L. Cave
It is often desired to develop the input threshold voltage of Transistor-Transistor-Logic (TTL) of two bass-emitter voltages (V,,) on technologies other than TTL. Some technologies such as Power SIMOS which combine bipolar and MOS devices do not allow the bipolar devices to be referenced to ground, thereby making it difficult to achieve the TTL input voltage. This restriction is the result of a P type substrate serving as the output of the circuit, thereby limiting all epitaxial regions (PNP bases and NPN collectors) to a voltage level at or near the positive supply voltage.
Figure 1 illustrates a conventional Darlington arrangement having a TTL input volltage of two V,,. If thresh- old sensing is accomplished with a sense element between the emitter of Q2 AND V,,. the input threshold is shifted by the amount required by the sense circuit, If threshold sensing is accomplished with a sense element between the collector of Q2 and V,,, the collector potential of Q2 must be lowered. A lower collector potential may result in a parasitic four layer latch (substrate, epitaxial, base, emitter) in those technologies using the substrate as the output.
Figure 2 illustrates a conventional NMOS input arrangement. If the voltage threshold of the NMOS device is made somewhat less than 0.7 volts, the circuit could be made TTL compatible by sensing with the sense ele- ment coupled between the drain of transistor Q3 and V,...