Load Impedance for Transistor Circuit
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Del.icio.us| IP.com Number | IPCOM000071581D |
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| Dated | Feb 1, 1970 UTC | ||
| Size | 2 page(s) (47.0 KB) | ||
| Disclosed by |
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Publication Summary
The drawing shows a portion of a monolithic circuit in which a transistor, operated in the reverse mode, is used as a load impedance of another transistor.| Country | United States |
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| Language | English (United States) |
| Related Person(s) |
(AUTHOR) Varadarajan, HD |
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Load Impedance for Transistor Circuit
The drawing shows a portion of a monolithic circuit in which a transistor, operated in the reverse mode, is used as a load impedance of another transistor.
Slice 1 of P type silicon has N type epitaxial layer 2 formed thereon. Transistors T1 and T2 are formed in an isolated pocket defined by diffused P type regions 3. Collectors of transistors T1 and T2 are electrically interconnected by buried subcollector region 4 of high N conductivity type. Emitter terminal 5, base terminal 6, and collector terminal 7 of T1 are connected to the remainder of the electrical circuit which can be a bistable circuit. Emitter terminal 9 of T2 is connected to a source of positive potential and the reverse avalanche breakdown characteristic of T2 is used as the load impedance of T1. If the base spreading resistance of T2 is sufficiently large, optional metallization 8 can be provided to short out collector-base junction of T2 to decrease the switching time of T2 without destroying the soft avalanche breakdown characteristic.
With this arrangement the monolithic circuit is much smaller than the case where a resistor or a series of diodes is used as the load impedance of T1. This is because T2 is smaller than resistors or diodes of the same impedance and also because it is formed within the same isolation pocket as T1.
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