Software Interrupt Emulation And Method To Provide Run Time Firmware Function Calls For POWER/PowerPC Processors In Native Mode
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Del.icio.us| IP.com Number | IPCOM000132036D |
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| Dated | Nov 29, 2005 UTC | ||
| Size | 2 page(s) (28.6 KB) | ||
| Disclosed by |
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Publication Summary
Disclosed is a method to implement software interrupt emulation on POWER/PowerPC (*) processor in native mode for runtime firmware function calls| Country | |
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| Language | English (United States) |
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Software Interrupt Emulation And Method To Provide Run Time Firmware Function Calls For POWER/PowerPC Processors In Native Mode
The system firmware reserves memory space near the end of the available system memory to load the program image of the run time firmware service function calls. The base address of this memory space is saved into the Hypervisor Special Purpose Register (HSPRG) 0. This firmware image has software interrupt vector offsets which are equally 256 bytes apart. Each software interrupt vector serves as an entry point to a specific firmware service function which the operating system (OS) may want to use at run time. Software interrupt vector 0, 0x100, 0x200, and 0x300 are reserved. This space will be initialized with the address of the context buffer per each processor. The first level interrupt handler of a software interrupt vector retrieves this address to save the content of volatile General Purpose Registers (GPRs). Each doubleword (8 bytes) holds an address. Therefore, this example implementation will support a system with 128 processors,
The assembly subroutine INT400 to make a software interrupt vector 0x400 call is shown belows:
INT400: mtspr HSPRG1, r1 # Save R1 mflr r1 # Set return address mtsrr0 r1 # into SRR0 mfmsr r1 # Set current context mtsrr1 r1 # into SRR1 ori r1, r1, 0x8000 # xori r1, r1, 0x8000 # Turn off EE-bit mtmsrd r1 # mfspr r1, HSPRG0 # Get base address addi r1, r1, 0x400 # add software interrupt vector offset mtlr r1 #...